1. Field of the Invention
The present invention relates to a method of manufacturing a multilayer structure, for example corresponding to an integrated circuit wafer, on a support by molecular bonding.
2. Description of the Related Art
For certain applications, it is desirable to form an integrated circuit wafer on a support. In particular, for applications in optics, the support should be insulating and transparent. It for example is glass. An example of application relates to the manufacturing of a transmissive display screen.
FIGS. 1A to 1C show simplified cross-section views of structures obtained at successive steps of a method of manufacturing an integrated circuit wafer on a support by molecular bonding.
FIG. 1A schematically shows an element 10 having an SOI (Silicon On Insulator) structure.
Element 10 comprises an initial support 12, for example, a single-crystal silicon substrate. Thickness es of initial support 12 is for example several hundred micrometers and is, for example, equal to approximately 700 μm. Initial support 12 may correspond to a cylinder having a diameter greater than some hundred millimeters, and is equal, for example, to approximately 200 mm or 300 mm. Initial support 12 comprises a planar surface 13 covered with an insulating layer 14, for example, made of silicon dioxide. Thickness e2 of insulating layer 14 is for example in the order of 1 μm. Insulating layer 14 is covered with an integrated circuit wafer 16. Integrated circuit wafer 16 comprises a stack of layers having active and/or passive electronic components and conductive tracks connecting these components. As an example, integrated circuit wafer 16 comprises a layer 18 of a semiconductor material, for example, single-crystal silicon, covering insulating layer 14 and having the active and/or passive electronic components, for example, transistors 20, formed inside and on top of it. Integrated circuit wafer 16 further comprises a stack of insulating layers 22, for example, made of silicon dioxide, covering silicon layer 18 and having tracks 24 and vias 26 of a conductive material, capable of coming into contact with the electronic components, formed therein. As an example, thickness e3 of wafer 16 is in the order of a few micrometers. The last insulating layer of stack 22 of insulating layers forms a planar upper surface 28 opposite to support 12.
FIG. 1B shows the structure obtained after the performing of a molecular bonding between surface 28 of element 10 and a final support 30. Final support 30 is made of a material different from silicon, for example, made of glass. Thickness ev of final support 30 is greater than several hundred micrometers, and is, for example, equal to approximately 700 μm. Final support 30 comprises a surface 32 applied against surface 28. Molecular bonding comprises creating a bond between surfaces 28 and 32 with no addition of external material (such as glue or an adhesive material). To achieve this, surfaces 28 and 32, properly cleaned, are placed in contact with each other at ambient temperature. A pressure may be locally exerted on support 30 to initiate the bonding. The propagating front of the bonded area then spreads from the initiation region over all the opposite surfaces.
FIG. 1C shows the structure obtained after the removal of initial support 12. The removal of initial support 12 may comprise a step of chem.-mech. polishing to remove most of initial support 12, followed by a step of selective chemical etching to remove the rest of initial support 12. Insulating layer 14 may be used as a stop layer on removal of initial support 12.
The method then generally carries on with the forming of conductive vias through insulating layer 14 and silicon layer 18 and connected to metal tracks 24 of integrated circuit wafer 16. The forming of these vias comprises photolithography steps, including steps where a resist layer covering insulating layer 14 is exposed to a radiation through a mask to reproduce the mask pattern on the resin layer. To achieve this, the exposure device, which particularly comprises the optical systems for forming the pattern in the resist layer, should be accurately placed with respect to integrated circuit wafer 16.
In an industrial scale manufacturing process, the photolithography steps should be carried out as fast as possible. To achieve this, the exposure device is previously adjusted so that the pattern to be transferred forms properly with no additional adjustment in the resin layer for an integrated circuit wafer which would have the expected dimensions.
However, deformations can be observed in integrated circuit wafer 16 after the bonding step. In particular, a narrowing is observed, that is, two marks formed on bonding surface 28 before the bonding step have come closer to each other after the bonding step.
Further, the relative deformations observed in integrated circuit wafer 16 in a plane parallel to surface 28 generally vary according to the considered direction. Thereby, the observed relative narrowing may vary between approximately 16 ppm and 24 ppm along the considered direction, parallel to surface 28.
An average deformation of 20 ppm can generally be compensated for by the exposure device. However, in certain cases, the average deformation may be too large to be compensated for by the exposure device. Further, it is not possible to correct, with the exposure device, relative deformation differences which vary along the considered direction. Thereby, there may be misalignments between the exposure device and the integrated circuit wafer during the photolithography steps carried out after the bonding.
A method of manufacturing by molecular bonding a multilayer structure, for example, corresponding to an integrated circuit wafer, on a support where deformations in the integrated circuit wafer which result from the bonding operation are decreased, or even suppressed, is thus needed.